1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a test mode.
2. Description of the Related Art
As a semiconductor integrated circuit having a test mode, for example, a technique disclosed in Japanese Unexamined Patent Application Publication No. Hei 2000-243797 is known. This semiconductor integrated circuit shifts to the test mode when a test command is inputted a plurality of times in a normal operation mode. Therefore, the semiconductor integrated circuit is prevented from shifting to the test mode accidentally in normal operation.
However, for example, when a plurality of tests are executed after the semiconductor integrated circuit is fabricated, it is necessary to input a command signal a plurality of times for each test. It is also necessary to input the command signal a plurality of times to shift an operation mode in the semiconductor integrated circuit from the test mode to the normal operation mode after each test is terminated. Hence, there is a problem that, when a plurality of the tests are executed successively, the command signal needs to be inputted many times, thereby increasing the test time.